1. Field of the Invention
The present invention relates to a semiconductor device and a skew adjusting method, and in detail to a skew adjusting technique between chips in circuits divided into the plural chips.
2. Description of the Related Art
Conventionally, in a memory controller, a reduction of a skew between an address signal and a data signal (hereinafter, called also as “between address and data”) has been realized by mounting every circuit composing the memory controller on one chip. However, there are quite a lot of cases in which an enough number of pins (number of external terminals) cannot be secured on one chip in accordance with improvements of functions according to complication, multifunction, and so on of functions, regardless of a multi-pin packaging in recent years.
When the memory controller is realized by being divided into plural chips, a skew adjusting between address and data becomes very hard. This becomes a factor disturbing the memory controller from being divided into plural chips.
Here, in a memory system having replaceable SDRAM modules, a method to adjust a clock skew generated according to a difference of memory capacities (load capacitance) by each SDRAM module, is proposed (for example, refer to Patent Document 1). In the method shown in the Patent Document 1, phase adjustments of clocks supplied to the SDRAM modules are performed by controlling a phase adjuster based on stored adjusting value setting information and memory capacity information obtained from the attached SDRAM modules. However, in the method shown in the Patent Document 1, it is necessary to set and store the adjusting value setting information and the memory capacity information beforehand, and therefore, it is difficult to flexibly correspond to arbitrary SDRAM module.
Besides, there is a case when it is impossible to mount the memory controller on one chip according to not only a restriction of number of pins held by the chip, but also a restriction of electric power consumption caused by an increase of a circuit scale and so on.
[Patent Document 1] Japanese Patent Application Laid-open No. 2003-271447